1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device such as a synchronous dynamic random-access memory (SDRAM). More particularly, the invention relates to an address selection circuit capable of quickly generating an address selection signal, and to a semiconductor memory device capable of high-speed access, including the first access in a burst access.
2. Description of the Related Art
FIG. 10 shows the structure of a conventional SDRAM, mainly showing the structure of the circuits that generate a column address selection signal from an externally input address signal, and omitting the circuits that generate a row address selection signal and perform data input and output.
The conventional SDRAM in FIG. 10 has six input transistor-transistor-logic buffers (TTL BUF) 10, five latch circuits 11, a mode register (REG) 12, a clock driver 13, a pair of delay circuits 14, 15 for timing control, a command decoder (DEC) 16, a column address counter control clock generator (CLK GEN) 17, a column address (COL ADDR) counter 18, a carry generator (CARRY GEN) 19, a burst length counter 110, a column address pre-decoder (COL ADDR PRE-DEC) 111, a column address decoder (COL ADR DEC) 112, and a memory cell array 113.
The input TTL buffers 10 input a clock signal CLK, a chip select command signal /CS, a row address strobe command signal /RAS, a column address strobe command signal /CAS, a write enable command signal /WE, and an address signal ADD, the slashes indicating signals that are active low. The command signals and the address signal are passed to the latch circuit 11. To indicate that they have been buffered, the signals input to the latch circuits 11 are denoted CSb, RASb, CASb, WEb, and ADD_BUF. The buffered address signal ADD_BUF may be a parallel multiple-bit signal.
FIG. 11A shows the structure of the latch circuits 11, while FIG. 11B indicates the meaning of transistor symbols. For the CASb latch circuit 11, for example, the input signal DIN in FIG. 11A is the CASb signal output from the /CAS input TTL buffer 10 in FIG. 10, the output signal denoted DOUT in FIG. 11A is the signal denoted CASINb in FIG. 10, and the output signal denoted DOUTb in FIG. 11A is the signal denoted CASIN in FIG. 10.
The latch circuit 11 in FIG. 11A comprises inverters 113, 114, 118, 119, 122, 123, 124, 125, n-channel transistors 116, 120, and p-channel transistors 117, 121. Transistors 116 and 117 form a transmission gate TG12; transistors 120 and 121 form a transmission gate TG13. Inverters 118 and 119 form a master latch circuit; inverters 122 and 123 form a slave latch-circuit.
FIG. 12 shows the structure of a one-bit section of the column address counter 18, comprising inverters 126, 127, 130, 131, 134, 135, 139, 140, 143, 144, 145, 146, n-channel transistors 128, 132, 138, 142, p-channel transistors 129, 133, 137, 141, and an exclusive-OR gate 136. Inverters 130 and 131 form a master latch circuit MFF1 for an externally input address bit; inverters 139 and 140 form a master latch circuit MFF for an internally generated address bit; inverters 143 and 144 form a slave latch circuit. Transistors 128 and 129 form a transmission gate TG14; transistors 132 and 133 form a transmission gate TG15. Transistors 137 and 138 form a transmission gate TG16; transistors 141 and 142 form a transmission gate TG17.
FIG. 13 is a timing diagram of the main signals illustrating the operation of the conventional SDRAM in FIG. 10 up to the generation of a column address selection signal. FIG. 13 shows an example of the signal waveforms when the burst length is four and the burst type is sequential. The operation of the conventional SDRAM up to the generation of the column address selection signal will be described below with reference to FIGS. 10-13.
The externally input clock signal CLK passes through the CLK input TTL buffer 10 and is input as a clock signal CLK_BUF to the clock driver 13. The clock driver 13 generates two clock signals with complementary logic at substantially the same time: a signal CLK_BUFD having the same logic as the input clock signal CLK, and a signal CLK_FFb having inverted logic, as shown in FIG. 13. Clock signal CLK_BUFD is input to timing control delay circuit 14, and clock signal CLK_FFb is input to the latch circuits 11.
The clock signal CLK_BUFD input to delay circuit 14 is delayed and becomes a control clock signal CLK_BUFD1 (FIG. 13). This control clock signal CLK_BUFD1 is input to the column address counter control clock generator 17 and the burst length counter 110.
The externally input command signal /CAS passes through the /CAS input TTL buffer 10 and is input as a command signal CASb to the CASb latch circuit 11.
The logic transitions of the externally input command signal /CAS occur at intervals longer than a setup time tSI and hold time tHI from rising edges of the externally input clock signal CLK (FIG. 13). More specifically, the command signal /CAS goes to the Low level earlier than a rising edge of the clock signal CLK by at least the setup time tSI and returns to the High level later than the rising edge of the clock signal CLK by at least the hold time tHI (FIG. 13). The other command signals /CS, /RAS and /WE are also input in this way.
In the CASb latch circuit 11 (FIG. 11A), when clock signal CLK_FFb is High, transmission gate TG12 is switched on and transmission gate TG13 is switched off. In this state, the input command signal CASb (DIN in FIG. 11A) is latched in the master latch circuit formed by inverters 118 and 119. When the externally input clock signal CLK goes to the High level, clock signal CLK_FFb goes to the Low level. In synchronization with the falling edge of clock signal CLK_FFb, transmission gate TG12 switches off and transmission gate TG13 switches on, so the command signal CASb is latched in the slave latch circuit formed by inverters 122 and 123 and becomes the output command signal CASIN (DOUTb in FIG. 11A) and its inverted logic signal CASINb (DOUT in FIG. 11A), which are input to the command decoder 16.
The command signals CASIN and CASINb are held and output continuously from the CASB latch circuit 11 until the next falling edge of clock signal CLK_FFb.
The command signals CASIN and CASINb are thus output continuously from the CASb latch circuit 11, starting slightly after the first rising edge of the externally input clock signal CLK after input of the external command signal /CAS begins, and continuing until slightly after the next rising edge of the externally input clock signal CLK. For example, CASIN goes to the High level following a rising edge of the externally input clock signal CLK, and goes to the Low level following the next rising edge of the externally input clock signal CLK, as shown in FIG. 13. The CSb, RASb, and WEb latch circuits 11 also operate in this way when command signals CSb, RASb, and WEb are input.
The command decoder 16 decodes the signals CSIN and CSINb received from the CSb latch circuit 11, the signals RASIN and RASINb received from the RASb latch circuit 11, the signals CASIN and CASINb received from the CASb latch circuit 11, and the signals WEIN and WEINb received from the WEb latch circuit 11, and outputs control signals RAS_CL, WE_CL, PRE_CL, MOD_CL, and CAS_CL. The SDRAM thereby enters an operating mode responsive to the command given by the input command signals /CS, /RAS, /CAS, and /WE.
Control signal MOD_CL goes High when a mode register command is input. Control signal RAS_CL goes High when a row active command is input. Control signal CAS_CL goes High when a read command is input. Control signals CAS_CL and WE_CL both go High when a write command is input. Control signal PRE_CL goes High when a precharge command is input. In FIG. 13, since control signal CAS_CL goes High, the SDRAM enters the read or write command operation mode.
Since the logic transitions of control signal CAS_CL occur in synchronization with the command signals CASIN and CASINb output from the CASb latch circuit 11, control signal CAS_CL goes High following the first rising edge of the externally input clock signal CLK and goes Low following the next rising edge of the externally input clock signal CLK, as shown in FIG. 13.
The externally input address signal ADD is received in the same way as the externally input command signal /CAS, passing through the address input TTL buffer 10 and being input as an address signal ADD_BUF to the ADD_BUF latch circuit 11.
The logic transitions of the externally input address signal ADD, like the logic transitions of the externally input command signal /CAS, occur at intervals longer than a setup time tSI and hold time tHI from rising edges of the externally input clock signal CLK (FIG. 13). More specifically, each bit of the address signal ADD goes to the High or Low level earlier than a rising edge of the clock signal CLK by at least the setup time tSI, and remains at that High or Low level for at least the hold time tHI from that rising edge of the clock signal CLK (FIG. 13).
In the ADD_BUF latch circuit 11 (FIG. 11A), when clock signal CLK_FFb is High, transmission gate TG12 is switched on and transmission gate TG13 is switched off. In this state, the input address signal ADD_BUF (DIN in FIG. 11A), like the command signal CASB, is latched in the master latch circuit formed by inverters 118 and 119. When the externally input clock signal CLK goes High, clock signal CLK_FFb goes Low. The address signal ADD_BUF is latched in the slave latch circuit formed by inverters 122 and 123 in synchronization with the falling edge of clock signal CLK_FFb, and becomes the output address signal AIN (DOUT in FIG. 11A), which is input to the column address counter 18 and the mode register 12.
The address signal AIN is held and output continuously from the ADD_BUF latch circuit 11 until the next falling edge of clock signal CLK_FFb.
The address signal AIN is thus output continuously from the ADD_BUF latch circuit 11, starting slightly after the first rising edge of the externally input clock signal CLK after input of the external address signal ADD begins, and continuing until slightly after the next rising edge of the externally input clock signal CLK. In FIG. 13, for example, AIN assumes a certain value AIN(i) in synchronization with a rising edge of the externally input clock signal CLK, and retains that value until the next rising edge of the externally input clock signal CLK.
The mode register 12 generates a Burst Type signal and a Burst Length signal. The Burst Type signal is input to the carry generator 19; the Burst Length signal is input to the carry generator 19 and the burst length counter 110. The burst length counter 110 generates a burst control signal (denoted BURST), which is input to the column address counter control clock generator 17.
The burst control signal (BURST) goes High in synchronization with the rising edge of the CAS_CL control signal, and returns to the Low level after a number of CLK_BUFD1 clock pulses have been counted, the number being given by the burst length set by the Burst Length signal. In FIG. 13, the burst length is four, so four CLK_BUFD1 clock pulses are counted.
The column address counter control clock generator 17 takes the logical AND of the burst control signal (BURST) and clock signal CLK_BUFD1. From the resulting logical AND signal and the CAS_CL control signal, the column address counter control clock generator 17 generates a control clock signal EXT-YCLK for use in generating the first column address selection signal Y-SEL(i) of the burst, and another control clock signal INT-YCLK for use in generating further column address selection signals Y-SEL(i+1), Y-SEL(i+2), and Y-SEL(i+3). The combined number of pulses of the control clock signals EXT-YCLK and INT-YCLK is equal to the length of the burst, e.g., four pulses in FIG. 13. Control clock signals EXT-YCLK and INT-YCLK are input to timing control delay circuit 15, column address counter 18, and carry generator 19.
The control clock signals EXT-YCLK and INT-YCLK are combined and delayed in delay circuit 15 and become a control clock signal YCLKD (FIG. 13), which is input to the column address decoder 112.
In the column address counter 18 (FIG. 12), when the address signal AIN is input from the ADD_BUF latch circuit 11, if the control clock signals EXT-YCLK and INT-YCLK are Low, transmission gates TG14 and TG16 are switched on and transmission gates TG15 and TG17 are switched off. In this state, the input address signal AIN is latched in master latch circuit MFF1. After the externally input clock signal CLK goes High, the control clock signal EXT-YCLK goes High. The address signal AIN is then latched in the slave latch circuit SFF and becomes the first output column address signal AY(i), which is input to the column address pre-decoder 111. The column address signal AY(i) is also output to the carry generator 19 and exclusive-OR gate 136 for use in the internal generation of the next column address signal AY(i+1).
The first column address signal AY(i) is thus the address signal AIN(i), which is input to the column address counter 18 from the ADD_BUF latch circuit 11 in synchronization with clock signal CLK_FFb, and output from the column address counter 18 in synchronization with control clock signal EXT-YCLK, as shown in FIG. 13.
In the conventional SDRAM, the address signal AIN(i), which is output from the ADD_BUF latch circuit 11 in synchronization with clock signal CLK_FFb, is latched in the column address counter 18 and output from the column address counter 18 in synchronization with the rising edge of the EXT-YCLK control clock signal, as described above. The column address counter control clock generator 17 generates the EXT-YCLK control clock signal by using the CLK_BUFD1 clock signal, which is delayed from clock signal CLK_BUFD by timing control delay circuit 14. This delay provides the column address counter 18 with a sufficient setup time, indicated as t11 in FIG. 13.
The carry generator 19 generates a carry signal (CARRY) from the first column address signal AY(i), the Burst Type signal, and the Burst Length signal in synchronization with the rising edge of the control clock signal EXT-YCLK input from the column address counter control clock generator 17. The carry signal is input to the column address counter 18 and used for the internal generation of the next column address signal AY(i+1).
The column address pre-decoder 111 pre-decodes the first column address signal AY(i), and sends a pre-decoded column address signal Pre-YADD(i) to the column address decoder 112.
The column address decoder 112 decodes the pre-decoded column address signal Pre-YADD(i) in synchronization with the rising edge of the control clock signal YCLKD input from timing control delay circuit 15, and generates a column address selection signal Y-SEL(i), as shown in FIG. 13, selecting a column of memory cells in the memory cell array 113.
In the column address counter 18 (FIG. 12), when the EXT-YCLK control clock signal is High and the first column address signal AY(i) is output, an internally generated column address signal AY(i+1), which is the logical exclusive-OR (the signal output from exclusive-OR gate 136) of the first column address signal AY(i) and the carry signal (CARRY) generated from column address signal AY(i), is latched in master latch circuit MFF.
When control clock signal EXT-YCLK goes Low, transmission gate TG15 is switched off. The first column address signal AY(i) continues to be held in the slave latch circuit SFF until control clock signal INT-YCLK goes High. In synchronization with the rising edge of control clock signal INT-YCLK, transmission gate TG16 is switched off and transmission gate TG17 is switched on. In this state, the internally generated column address signal AY(i+1) is latched in the slave latch circuit SFF, from which it is output to the column address pre-decoder 111, the carry generator 19, and exclusive-OR gate 136 in the column address counter 18 for use in the internal generation of the next generated column address signal AY(i+2).
The column address pre-decoder 111 pre-decodes the internally generated column address signal AY(i+1), and sends a pre-decoded column address signal Pre-YADD(i+1) to the column address decoder 112.
The column address decoder 112 decodes the pre-decoded column address signal Pre-YADD(i+1) in synchronization with the rising edge of the control clock signal YCLKD input from timing control delay circuit 15, and generates a column address selection signal Y-SEL(i+1) corresponding to the internally generated column address signal AY(i+1), as shown in FIG. 13, to select another column in the memory cell array 113.
The column address counter 18 internally generates and outputs the following column address signals AY(i+2) and AY(i+3) in the same way as column address signal AY(i +1). The column address decoder 112 generates column address selection signals Y-SEL(i+2) and Y-SEL(i+3) corresponding to these column address signals AY(i+2) and AY(i+3).
In the conventional SDRAM, the column address counter. 18 generates column address signals AY in synchronization with rising edges of control clock signals EXT-YCLK and INT-YCLK, and the column address decoder 112 generates the column address selection signal Y-SEL in synchronization with rising edges of control clock signal YCLKD, which is generated by delaying control clock signals EXT-YCLK and INT-YCLK in timing control delay circuit 15. The column address decoder 112 has a setup time requirement, indicated as t12 in FIG. 13; the purpose of delaying clock signal YCLKD with respect to the EXT-YCLK and INT-YCLK clock signals is to satisfy this set-up time requirement.
To summarize, in the conventional SDRAM, the externally input address signal ADD is latched in the ADD_BUF latch circuit 11 in synchronization with the externally input clock signal CLK, and an internal address signal AIN is output; this address signal AIN is latched in the column address counter 18 in synchronization with control clock signals EXT-YCLK and INT-YCLK generated by delaying the clock signal CLK, and a column address signal AY is output; the column address signal AY is decoded in the column address pre-decoder 111 and column address decoder 112 in synchronization with a control clock signal YCLKD generated by delaying control clock signals EXT-YCLK and INT-YCLK, and a column address selection signal Y-SEL is generated. The control clock signals are delayed in order to provide adequate setup times t11 and t12 for the column address counter 18 and the column address decoder 112.
An SDRAM performs high-speed burst access by using pipeline and prefetch techniques. These techniques speed up accesses to the memory cell array after the first access in the burst, but they do not speed up the first access. To provide sufficient time for the first access, the first access is delayed by a certain number of clock cycles with respect to the column address strobe, creating what is known as a CAS latency. SDRAM devices with high clock frequencies require increasingly large CAS latencies. Although the apparent first access time, exclusive of the CAS latency, may be short, the key to true high-speed operation is to obtain rapid first access including the CAS latency, by decreasing the CAS latency.
In the conventional SDRAM, the internal clock signals are successively delayed in order to obtain setup times t11 and t12 and to assure stable internal operation, and the internal circuits operate on the delayed clock signals. If the CAS latency is decreased, these clock signal delays limit the maximum operating frequency and become an obstacle to high-speed operation. Accordingly, in a conventional SDRAM, the problem in achieving high-speed access, including the first access, is how to reduce the delay of the internal clock signals and stabilize internal operations at the same time.
An object of the present invention is to provide an address selection circuit capable of quickly generating an address selection signal, and a synchronous semiconductor memory device capable of high-speed access, including the first access in a burst access.
The invented address selection circuit receives a clock signal and an address signal, outputs the received address signal directly as a first internal address signal, generates a second internal address signal from the received address signal in synchronization with the clock signal, and generates the address selection signal first from the first internal address signal, then from the second internal address signal. Output of the first internal address signal starts quickly because the first internal address signal is not synchronized to the clock signal. The invented address selection circuit can accordingly generate the address selection signal more quickly than if it relied entirely on synchronous internal address signals, as in the prior art. In a burst access, even the first address selection signal can be generated relatively quickly.
In a preferred embodiment of the invention, the received address signal passes through a first switching element on a first path for output as the first internal address signal. The received address signal is also latched and output through a second switching element on a second path as the second internal address signal. While the address selection signal is being generated from the first internal address signal, the first switching element is switched on and the second switching element is switched off. The first switching element is then switched off and the second switching element is switched on in synchronization with the clock signal, after which the address selection signal is generated from the second internal address signal.
The preferred embodiment also receives a command signal and processes it in a similar fashion, outputting the received command signal directly as a first (asynchronous) internal command signal, and generating a second internal command signal from the received command signal in synchronization with the clock signal. The first and second internal command signals are used to select between the first and second internal address signals.
The received address signal may be latched in synchronization with an internal clock signal that is generated from the received clock signal only while the address signal is being received, to avoid unnecessary latching operations during the later stages of a burst access, when the address signal is not being received.